Yingnan Zhao

Yingnan Zhao is currently a Ph.D. candidate from the Department of Electrical and Computer Engineering at George Washington University. He will join the Department of Computer Engineering at the University of Texas at San Antonio as a tenure-track Assistant Professor in Fall 2026. His research focuses on the design of high-performance, energy-efficient, and resilient algorithm hardware co-design architecture for the next AI generation acceleration. His work lies at the intersection of computer architecture, AI accelerators, graph neural networks, and large language models. His research investigates architectural techniques that improve scalability, hardware utilization, and data reuse for emerging machine learning workloads. His recent research explores accelerator architectures for graph neural network inference, including both static and dynamic graph models. He is also interested in architectural support for large-scale deep learning models and large language model workloads. His research work has frequently appeared in prestigious journals and conferences, including TPDS, TCAD, TSUSC, DAC, DATE, and ICCD.

Research Interests

Computer Architecture, High-Performance Computing, Algorithm-Architecture Co-Designs, Domain Specific Architectures for Emerging AI applications, Large Language Models, Graph Neural Networks, and Deep Learning.

Prospective Students

We are always expecting self-motivated and hardworking students. Please contact me with your CV and Transcripts if you are interested in my work or pursuing a Ph.D. degree.

📧 Email: yzhao96@gwu.edu

News

[April. 2026] One paper is accepted by IEEE Transactions on Parallel and Distributed Systems