Publications

You can also find my articles on my Google Scholar profile.

Journal Papers

[J-4] Y. Zhao, K. Wang, and A. Louri, "Bal-DGCN: A Hardware Acceleration Framework for Balanced Computational Efficiency in Dynamic Graph Convolutional Networks (DGCNs)," accepted by IEEE Transactions on Parallel and Distributed Systems (TPDS), April 2026.

[J-3] K. Wang, Y. Zhao, and A. Louri, "FORT-GCN: A Fault-tolerant and Adaptive Accelerator Design for Efficient Graph Convolutional Network Inference," in ACM Transactions on Embedded Computing Systems (TECS), July 2025.

[J-2] Y. Zhao, K. Wang, and A. Louri, "HS-GCN: A High-performance, Sustainable, and Scalable Chiplet-based Accelerator for Graph Convolutional Network Inference," in IEEE Transactions on Sustainable Computing (TSUSC), May 2025.

[J-1] Y. Zhao, K. Wang, and A. Louri, "OPT-GCN: A Unified and Scalable Chiplet-based Accelerator for High-Performance and Energy-Efficient GCN Computation," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), May 2024.

Conference Papers

[C-4] Ke Wang, Yingnan Zhao, and Ahmed Louri, "FORT-GCN: A Fault-tolerant and Adaptive Accelerator Design for Efficient Graph Convolutional Network Inference," in Proceedings of the 2025 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Taipei, Taiwan, September 28 – October 3, 2025.

[C-3] Yingnan Zhao, Ke Wang, and Ahmed Louri, "A High-performance and Flexible Accelerator for Dynamic Graph Convolutional Networks," in Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE), Lyon, France, March 31 – April 2, 2025. (Accept rate: 25%)

[C-2] Yingnan Zhao, Ke Wang, Jiaqi Yang, and Ahmed Louri, "An Efficient Hardware Accelerator Design for Dynamic Graph Convolutional Network (DGCN) Inference," in Proceedings of the ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, June 23-27, 2024. (Accept rate: 23%)

[C-1] Yingnan Zhao, Ke Wang, and Ahmed Louri, "FSA: An Efficient Fault-Tolerant Systolic Array Based DNN Accelerator," in Proceedings of the 40th IEEE International Conference on Computer Design (ICCD), Lake Tahoe, CA, October 23-26, 2022. (Accept rate: 30%)